荷兰专利NL2025812A Boost half-bridge inverter and control circuit and method therefor

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39 AO 20.06.1082 NL Abstract The present invention discloses a boost half—bridge inverter and a control circuit and method therefor, and pertains to the field of power electronic converter. In the inverter 5 in the present invention, one end of the inductor Ll is connected to one end of an input power supply, and the other end of the inductor Ll is connected to the anode of a diode D1; the cathode of the diode D1 is connected to the end A of a power switching transistor S1, the cathode of a diode D2, and one end of a capacitor C1; the anode of the diode D2 is connected to the end A of a power switching transistor S2; the other end of 10 the capacitor C1 is connected to one end of a capacitor C2; the anode of a diode D3 is connected to the end C of the power switching transistor S2 and the other end of the capacitor C2; and the cathode of the diode D3 is connected to the end C of the power switching transistor S1 and the other end of the input power supply. To resolve prior—art problems that a boost inverter needs many switching devices and it is complex to 15 control the boost inverter, the inverter in the present invention is highly integrated, has a simple structure, is easy to control, and has a relatively high boost transformation ratio.
公开号:NL2025812A
申请号:NL2025812
申请日:2020-06-11
公开日:2020-12-22
发明作者:Hu Xuefeng；Yu Zhixiang；Cheng Yu；Liu Xing；Zhang Meng；Dai Guanjun
申请人:Univ Anhui Technology；
IPC主号:

专利说明:

1 AO 20.06.1082 NL BOOST HALF-BRIDGE INVERTER AND CONTROL CIRCUIT AND METHODTHEREFOR
TECHNICAL FIELD The present invention relates to the field of power electronic converter, and specifically, to a boost half-bridge inverter and control circuit and method therefor.
BACKGROUND With the rapid development of new energy generation systems, there are increasingly high requirements on performance of inverters. grid-connected inverters are the main interface device of power grids and photovoltaic arrays, and performance of the grid- connected inverter determines the performance of the entire photovoltaic power generation system. Therefore, the inverter develops towards high reliability, high power density, and high efficiency.
The conventional bridge inverter features simple topology and low costs, and therefore is widely applied. However, there is a shoot through problem between upper and lower switching transistors of the same bridge arm of the inverter, which reduces system reliability. To prevent shoot through, a dead zone needs to be added between drive signals. However, due to control of dead time, low-order harmonic appears during grid connection, resulting in distortion of the output current waveform and affecting output power quality, and additional conduction and reverse recovery loss are also caused due to the freewheeling of the switching diode body. In addition, the control of the dead time also limits implementation of high-frequency conversion.
Therefore, the dual-buck half-bridge inverter is an inverter topology that is widely studied and applied in recent years. The topology includes two unidirectional buck circuits, and there is no shoot through problem between power transistors of the bridge arm of the conventional inverter. In addition, the freewheeling diode is an independent diode, which resolves the reverse recovery problem of the switching diode body. In this way, selection of power tubes and freewheeling diodes can be optimized, which reduces the switching loss, and is suitable for small-scale low-power conversion. However, the input direct current voltage of the dual-buck half-bridge inverter has low utilization, the
2 AO 20.06.1082 NL maximum voltage output by a bridge arm is only half of the input direct current voltage, and a higher input direct current voltage is required for a scenario in which a high voltage needs to be output.
Chinese patent application with publication No. CN107834886A and publication date March 23, 2018 discloses a single-stage boost inverter and a control method therefor. A boost inductor is added to the inpat direct current power supply side, which not only implements boost, but also avoids complex feature of two-stage circuit. Disadvantages of the inverter are as follows: The inverter makes drastic changes to the full-bridge inverter to implement a boost function of the inverter, but many switching devices are used, which increases the circuit size and loss, and reduces efficiency of the inverter. In the prior art, a dual-buck inverter is studied in many literatures such as (1) a paper named "Half-cycle Current Modulation Method for Dual-buck Voltage Source Inverter”, written by Wang Zan, Xiao Lan, et al, and published in Transactions of China Electrotechnical Society vol. 22, No. 5 in May 2007; and (2) a paper named "Hysteresis Current Controlled Dual-buck Inverter, written by Hong Feng and Liu Jun, and published in Transactions of China Electrotechnical Society vol. 19, No. 8 in August
2004. All of the foregoing papers involve the buck inverter, but application scenarios are limited, and therefore extensive requirements cannot be met.SUMMARY
1. Technical problem to be resolved in the present invention To resolve the technical problem of the low boost ratio of the boost inverter in the prior art, the present invention provides a boost half-bridge inverter and a control circuit and method therefor. The inverter in the present invention is highly integrated, can implement boost inversion, has a stable alternating current output, and can achieve a relatively high boost transformation ratio.
2. Technical solutions To resolve the foregoing problem, the technical solutions provided in the present invention are as follows:
3 AO 20.06.1082 NL According to a first aspect, the present invention provides a boost half-bridge inverter, including power switching transistors S$; and S», diodes Dy, D2, and Ds, an inductor Lj, and capacitors C and Cs», where one end of the inductor Ly is connected to one end of the input side, and the other end of the inductor L; is connected to the anode of the diode Dy; the cathode of the diode D; is connected to the end A of the power switching transistor S1, the cathode of the diode Da, and one end of the capacitor Cy; the end C of the power switching transistor $, the cathode of the diode D3, and the other end of the input side are connected to a node a; the anode of the diode D> and the end A of the power switching transistor S, are connected to a node b; the other end of the capacitor C and one end of the capacitor C; are connected to a node c; the anode of the diode Ds is connected to the end C of the power switching transistor S» and the other end of the capacitor Cy; and the nodes a, b, and c form the output side.
Further, the output side is connected to the input side of a filter, and the output side of the filter is connected to a load or a power grid. Further, the power switching transistors 5; and S5 are IGBTs or MOSEFETS.
Further, the one end of the input side is connected to the positive electrode of the direct current power supply, and the other end of the input side is connected to the negative electrode of the direct current power supply.
4 AO 20.06.1082 NL Further, the filter is a filter], the filter] includes filter inductors L, and L3 and a filter capacitor Co, one end of the filter inductor L; is connected to the node a, the other end of the filter inductor L, is connected to one end of the filter inductor LZ; and one end of the filter capacitor Co, the other end of the filter capacitor Co is connected to the node c, the other end of the filter inductor Ls is connected to the node b, and the one end of the filter capacitor Co and the node c form the output side of the filter.
Further, the filter is a filterll, the filterll includes filter inductors L,; and L3;, one end of the filter inductor L,; is connected to the node a, the other end of the filter inductor Ly is connected to one end of the filter inductor L31. the other end of the filter capacitor Ls; is connected to the node b, and the one end of the filter inductor Ls; and the node c form the output side of the filter.
Further, the filter is a filter, the filter includes filter inductors Loo, Lagi, and Lao and a filter capacitor Co;, one end of the filter inductor Za is connected to the node a, the other end of the filter inductor Lao is connected to one end of the filter inductor Lig, one end of the filter inductor Lsg;, and one end of the filter capacitor Cp), the other end of the filter inductor L391 is connected to the node b, the other end of the filter capacitor Cot is connected to the node c‚ and the other end of the filter inductor Lig; and the node c form the output side of the filter.
According to a second aspect, the present invention provides a control circuit for the boost half-bridge inverter corresponding to the first aspect, where the voltage on the output side of the filter is used as a feedback voltage, and is compared with a given voltage Ue to obtain an error value, the error value is adjusted by a regulator, and then is compared with a triangular wave to generate a pulse signal, and the pulse signal is input into ends B of the power switching transistors S$; and S$. According to a third aspect, the present invention provides a control method for the boost half-bridge inverter corresponding to the first aspect, where bipolar modulation waveforms are input into the ends B of the power switching transistors S$; and $5, and the following working modes are included: When the modulation wave is greater than
AO 20.06.1082 NL the carrier, the power switching transistor Sj is controlled to be conducted, 5; is controlled to be cut off, the diodes D, and D: are controlled to be conducted, and Dj is controlled to be cut off; the input side, the inductor L;, the diode D,, and the power switching transistor S; form a loop to charge the inductor L;; the power switching 5 transistor Sy. the nodes a and b on the output side, and the diode D, form a loop; and the capacitor Cy, the power switching transistor Si, and the nodes a and c on the output side form a loop to supply power to the output side; or when the modulation wave is less than the carrier, the power switching transistor S; is controlled to be conducted, S; is controlled to be cut off, the diode D5 is controlled to be conducted, and D: is controlled to be cut off; the power switching transistor S,, the nodes a and b on the output side, and the diode D3 form a loop; and the power switching transistor 55, the nodes a and c on the output side, and the capacitor C, form a loop to supply power to the output side.
Further, the following working mode is included: When the modulation wave is less than the carrier, the power switching transistor $ is controlled to be conducted, S; 1s controlled to be cut off, the diode Ds; is controlled to be conducted, and D: is controlled to be cut off; the input side, the inductor L,, the diode Di, and the capacitors Cy and Ca, and the diode Ds form a loop; the power switching transistor Sz, the nodes a and b on the output side, and the diode D3 form a loop; and the power switching transistor Sy, the nodes a and c on the output side, and the capacitor C form a loop to supply power to the output side.
Further, the voltage ratio G of the output side to the input side is as follows: G=Vm oy |+ BR, Un 4 L ‚ where Uom represents the voltage amplitude on the output side, Ui, represents the voltage amplitude on the input side, m represents the modulation ratio, Ts represents the modulation cycle, and Ro represents the equivalent impedance value of the load or power grid connected to the output side of the filter.
6 AO 20.06.1082 NL Further, the control method involves single-voltage closed-loop control.
The voltage on the output side of the filter is selected as a feedback voltage, and is compared with a given voltage User to obtain an error value, and the error value is adjusted by a regulator, and then is compared with a triangular wave to generate a pulse signal to control conduction and cut-off of the power switching transistors S and $:, so that the power switching transistors S; and $; work in a complementary state.
According to a fourth aspect, the present invention provides a boost half-bridge inverter, including power switching transistors Si, 52. and Ss, diodes Dy, D,, and Ds, an inductor L,, and capacitors C; and C3, where one end of the inductor L; is connected to one end of the input side, and the other end of the inductor L, is connected to the anode of the diode Dj and the end A of the power switching transistor Ss;
the cathode of the diode D; is connected to the end A of the power switching transistor Si, the cathode of the diode D;, and one end of the capacitor Ci; the end C of the power switching transistor Sy, the cathode of the diode D3, the end C of the power switching transistor Ss, and the other end of the input side are connected to a node a; the anode of the diode D> and the end A of the power switching transistor S, are connected to a node b;
the other end of the capacitor C and one end of the capacitor C; are connected to a node c; the anode of the diode D5 is connected to the end C of the power switching transistor S; and the other end of the capacitor C3; and the nodes a, b, and c form an output side.
7 AO 20.06.1082 NL Further, the output side is connected to the input side of a filter, and the output side of the filter is connected to a load or a power grid. Further, the power switching transistors Sy, Sz, and Sz are IGBTs or MOSEFETs.
Further, the one end of the input side is connected to the positive electrode of a direct current power supply, and the other end of the input side is connected to the negative electrode of the direct current power supply.
Further, the filter is a filter, the filter] includes filter inductors Ly and L3 and a filter capacitor Co, one end of the filter inductor L; is connected to the node a, the other end of the filter inductor L, is connected to one end of the filter inductor Lz and one end of the filter capacitor Co, the other end of the filter capacitor Co is connected to the node c, the other end of the filter inductor Ls is connected to the node b, and the one end of the filter capacitor Co and the node c form the output side of the filter.
Further, the filter is a filterll, the filterH includes filter inductors L,; and L3;, one end of the filter inductor L,; is connected to the node a, the other end of the filter inductor Ly is connected to one end of the filter inductor Lz, the other end of the filter capacitor Ls; is connected to the node b, and the one end of the filter inductor Ls; and the node c form the output side of the filter.
Further, the filter is a filter, the filter includes filter inductors Loo, Lagi, and Lag and a filter capacitor Co;, one end of the filter inductor Za is connected to the node a, the other end of the filter inductor Ly; is connected to one end of the filter inductor Lig, one end of the filter inductor Lao. and one end of the filter capacitor Cp), the other end of the filter inductor La391 is connected to the node b, the other end of the filter capacitor Coy Is connected to the node ¢, and the other end of the filter inductor Lig; and the node c form the output side of the filter.
According to a fifth aspect, the present invention provides a control circuit for the boost half-bridge inverter corresponding to the fourth aspect, where the voltage on the output
8 AO 20.06.1082 NL side of the filter is used as a feedback voltage, and is compared with a given voltage Uref to obtain an error value, the error value is adjusted by a regulator, and then is compared with a triangular wave to generate a pulse signal, and the pulse signal is input into ends B of the power switching transistors Sy, 55, and Ss.
According to a sixth aspect, the present invention provides a control method for the boost half-bridge inverter corresponding to the fourth aspect, where unipolar modulation waveforms are input into the ends B of the power switching transistors 57, S$», and $3, and the following working modes are included: in the positive half cycle in which the output voltage u, is greater than 0, when the modulation wave is greater than the carrier, the power switching transistors Ss and Sy are controlled to be conducted, $ is controlled to be cut off, and the diodes Dy, D,, and Dj are controlled to be cut off; the input side, the inductor L;, and the power switching transistor S| form a loop; and the power switching transistor Sy, the capacitor Cy, and the nodes a and c on the output side form a loop; or when the modulation wave is less than the carrier, the power switching transistors Sy, Sa, and Ss are controlled to be cut off, the diode D3 is controlled to be conducted, and the diodes D; and D are controlled to be cut off; and the nodes a and c on the output side, the diode D3, and the capacitor €: form a loop; or in the negative half cycle in which the output voltage u, is less than 0, when the modulation wave is greater than the carrier, the power switching transistors 52 and $3 are controlled to be conducted, S| is controlled to be cut off, and the diodes Dy, D,, and Ds are controlled to be cut off; the input side, the inductor L;, and the power switching transistor $3 form a loop; and the power switching transistor S,, the nodes b and c on the output side, and the capacitor C: form a loop; or when the modulation wave is less than the carrier, the power switching transistors Sy, Sa, and S; are controlled to be cut off, the diode D and Ds are controlled to be cut off, and the diode D; is controlled to be conducted; and the diode Dy, the capacitor Cy, and the
9 AO 20.06.1082 NL nodes b and c on the output side form a loop. Further, the following working mode is included: When the modulation wave is less than the carrier, the power switching transistors $;, 3S», and 3 are controlled to be cut off, both the diodes D; and Ds are controlled to be conducted, and the diode D; is controlled to be cut off; the input side, the inductor Ly, the diode D}, the capacitor Cy, the capacitor C,, and the diode D3 form a loop; and the nodes a and c on the output side, the diode Ds, and the capacitor C; form a loop.
Further, the following working mode is included: When the modulation wave is less than the carrier, the power switching transistors Sj, 52, and S3 are controlled to be cut off, and all of the diodes Dy, Ds, and D3 are controlled to be conducted; the input side, the inductor Ly, the diodes D;and Ds, and the capacitors C and C; form a loop; and the diode D;, the capacitor C), and the nodes b and c on the output side form a loop. Further, the control method involves single-voltage closed-loop control. The voltage on the output side of the filter is selected as a feedback voltage, and is compared with a given voltage Ue to obtain an error value, and the error value is adjusted by a regulator, and then is compared with a triangular wave to generate a pulse signal to control conduction and cut-off of the power switching transistors Sy, Sz, and Ss.
3. Beneficial effects Compared with the prior art, the technical solutions provided in the present invention have the following beneficial effects: (1) According to the boost half-bridge inverter and the control method therefor in the present invention, boost inversion can be implemented, a stable alternating current output is provided, and a relatively high boost transformation ratio can be achieved.
10 AO 20.06.1082 NL (2) The boost half-bridge inverter in the present invention is an integrated inverter in which the number of components is greatly reduced. Therefore, system costs are reduced, integration is improved, and the circuit occupies small space.
(3) According to the boost half-bridge inverter and the control method therefor in the present invention, a high boosting ability is provided, and boosting and inversion functions can be implemented by controlling conduction and cut-off of the two power switching transistors §; and S>. When the boost half-bridge inverter is applied to the photovoltaic field, the voltage of a solar panel can be converted and output, which has advantages such as reduced circuit components, a simple circuit structure, and high power conversion efficiency. (4) According to the boost half-bridge inverter and the control method therefor in the present invention, the disadvantage that the conventional two-stage boost inverter has a complex circuit is overcome, and a case in which current discontinuity occurs in a conventional dual-buck circuit is avoided. In this application, due to the function of the capacitors C) and C3, the output can store energy or freewheel. The output waveform is continuous, and the waveform quality is good. The boost half-bridge has advantages such as a simple circuit structure, a simple control solution, fewer power devices, high efficiency, low costs, low switching loss, long working life, and high integration. (5) According to the boost half-bridge inverter and the control method therefor in the present invention. In the conventional series two-stage boost inverter, a filter needs to be disposed at the output end of the first-stage boost inverter, and a filter also needs to be disposed at the output end of the second-stage inverter. The filter occupies large space and is cumbersome in design, which undoubtedly increases the size of the entire circuit and circuit design costs. The boost inverter in this application overcomes the foregoing disadvantages, needs only one filter, and occupies small space.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of the circuit structure according to Embodiment 1 of the present invention;
11 AO 20.06.1082 NL FIG. 2 shows a preferred implementation of FIG. 1; FIG. 3 shows a first preferred implementation of FIG. 2; FIG. 4 shows a second preferred implementation of FIG. 2; FIG. 5 shows a third preferred implementation of FIG. 2; FIG. 6 is a schematic diagram of a working status of the circuit structure in mode 1 according to Embodiment 4; FIG. 7 is a schematic diagram of a working status of the circuit structure in mode 2 according to Embodiment 4; FIG. 8 is a schematic diagram of a working status of the circuit structure in mode 3 according to Embodiment 4; FIG. 9 is a diagram of a waveform input into the end B of the power switching transistor in the circuit structure according to Embodiment 4; FIG. 10 is a working sequence diagram of the circuit structure according to Embodiment 4;
FIG. 11 is a simulation waveform diagram of the current of each inductor when the filtert is selected in the circuit structure according to Embodiment 4; FIG. 12 1s a simulation waveform diagram of eth output voltage z4, when the filterl is selected in the circuit structure according to Embodiment 4; FIG. 13 is a simulation waveform diagram of voltages Uc; and Ug; at both ends of each of capacitors C and C: when the filtert is selected in the circuit structure according to Embodiment 4; FIG. 14 is a schematic diagram oef th circuit structure according to Embodiment 5 of the present invention; FIG. 15 shows a preferred implementation of FIG. 14;
FIG. 16 shows a first preferred implementation of FIG. 15; FIG. 17 shows a second preferred implementation of FIG. 15; FIG. 18 shows a third preferred implementation of FIG. 15; FIG. 19 is a schematic diagram of the working status of the circuit structure in mode a according to Embodiment 5;
FIG. 20 1s a schematic diagram of the working status of the circuit structure in mode b according to Embodiment 5; FIG. 21 is a schematic diagram of the working status of the circuit structure in mode ¢
12 AO 20.06.1082 NL according to Embodiment 5; FIG. 22 is a schematic diagram of the working status of the circuit structure in mode d according to Embodiment 5; FIG. 23 is a schematic diagram of the working status of the circuit structure in mode e according to Embodiment 5; FIG. 24 is a schematic diagram of the working status of the circuit structure in mode f according to Embodiment 5; FIG. 25 is a diagram of the waveform input into the end B of the power switching transistor in the circuit structure according to Embodiment 5; FIG. 26 is a schematic diagram of the control circuit of the circuit structure according to Embodiment 1; FIG. 27 1s a schematic diagram of the control circuit of the circuit structure according to Embodiment 5; FIG. 28 is a sequence diagram of the working status of the circuit structure in the positive half cycle in which the output voltage u, is greater than () according to Embodiment 5; and FIG. 29 is a sequence diagram of the working status of the circuit structure in the negative half cycle in which the output voltage u, is less than 0 according to Embodiment 5.
DESCRIPTION OF EMBODIMENTS To further understand content of the present invention, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are merely intended to explain the related invention, and are not intended to limit the invention. In addition, It should also be noted that for ease of description, only parts related to the invention are shown in the accompanying drawings. It should be noted that the embodiments of this application and features in the embodiments may be combined with each other provided that there is no conflict.
The voltage on the output side of the filter is denoted as an output voltage u,, and a corresponding output voltage amplitude is Um. Power switching transistors Si, Sz, and
13 AO 20.06.1082 NL $3 can be IGBTs or other power switching transistors such as MOSEFETs. When IGBTs are used, the end A, the end B, and the end C of each of the power switching transistors 51, S2, and S3 respectively correspond to the collector, the base, and the emitter of each of the power switching transistors Sy, $2, and S3. When MOSEFETS are used, the end A, the end B, and the end C of each of the power switching transistors S, $2, and S3 respectively correspond to the drain electrode, the gate electrode, and the source electrode of each of the power switching transistors Sy, $2, and 3. One end of the input side of the boost half-bridge inverter in the present invention is connected to the positive electrode of a direct current power supply, and the other end of the input side is connected to the negative electrode of the direct current power supply. There are many kinds of direct current power supplies. The direct current power supply can be determined based on the specific application mode, scenario, or the field, and is not limited by the several cases enumerated in the present invention.
Only several limited implementations are enumerated in the present invention. Based on actual application requirements, the technical solutions of the present invention can be widely popularized and applied, for example, to the photovoltaic field, the energy storage battery field, air conditioners, electric tools, sewing machines, televisions, washing machines, range hoods, refrigerators, fans, lighting, and other household appliances or other feasible scenarios or fields. Cars are very popular nowadays, and the boost inverter provided in the present invention can be used to connect batteries to drive electric appliances and various tools to work In travel or business trips. An on-board inverter output by the cigarette lighter has a power specification of 20 W, 40 W, 80 W, or 120 W to 150 W. The boost inverter in the present invention is manufactured into a power converter. the input side of the power inverter is connected to the output side of the cigarette lighter, and household electrical appliances are connected to the output side of the power converter for use in a car. For example, available electric appliances include electric tools, on-board refrigerators, and various traveling, camping, and medical emergency appliances. In this case, the cigarette lighter serves as the direct current power supply described in the
14 AO 20.06.1082 NL present invention, and the amplitude of the direct current power supply is U,. In the document of the present invention, Uj, has the same meaning as U.
Embodiment 1 FIG. 1 is a schematic structural diagram of the circuit topology in the present invention.
This embodiment provides a boost half-bridge inverter, including power switching transistors St and 2, diodes Dy, D», and Ds, an inductor Lj, and capacitors C; and Cs. One end of the inductor L, is connected to one end of the input side, and the other end of the inductor L; is connected to the anode of the diode Dy; the cathode of the diode D; 1s connected to the end A of the power switching transistor Si, the cathode of the diode D,, and one end of the capacitor Cj; the end C of the power switching transistor S;, the cathode of the diode D3, and the other end of the input side are connected to a node a; the anode of the diode D- and the end A of the power switching transistor S, are connected to a node b; the other end of the capacitor C and one end of the capacitor C» are connected to a node c; the anode of the diode Ds is connected to the end C of the power switching transistor S$; and the other end of the capacitor C+; and the nodes a, b, and c form the output side. In comparison with the conventional inverter, the technical solution of the present invention achieves both an inversion effect and a boost effect. In comparison with the conventional boost inverter combining a DC-DC converter and an inverter, in terms of the circuit topology structure, the technical solution of the present invention does not
15 AO 20.06.1082 NL need a large-size filter to stabilize the output voltage of the DC-DC converter, and includes fewer circuit components, has a lower loss, occupies smaller space, has lower costs, and is easy to be popularized and applied. In terms of the control circuit, unlike the conventional boost inverter combining a DC-DC converter and an inverter that needs two control loops for control, the technical solution of the present invention simplifies the control method, and requires only one control loop to achieve a boost inversion effect.
Embodiment 2 To further filter out harmonics or clutter on the output side, this embodiment is based on Embodiment 1. FIG. 2 is a schematic structural diagram of a preferred manner of FIG.
1. The output side is connected to the input side of a filter, and the output side of the filter is connected to a load or a power grid. Various filters can be selected. Three filters are enumerated herein to explain and describe content of the technical solutions of the present invention. In the first case, FIG. 3 is a schematic structural diagram of the circuit topology in which the filter in FIG. 2 is a filter]. The filter is a filter], and the filter] includes filter inductors Ly and L3 and a filter capacitor Co. One end of the filter inductor L; is connected to the node a, the other end of the filter inductor L is connected to one end of the filter inductor L3 and one end of the filter capacitor Co, the other end of the filter capacitor Co is connected to the node c‚ the other end of the filter inductor Lj is connected to the node b, the one end of the filter capacitor Co and the node c form the output side of the filter, and Ro represents an equivalent impedance value of the load or power grid connected to the output side of the filter. In the second case, FIG. 4 is a schematic structural diagram of the circuit topology in which the filter in FIG. 2 is a filter. The filter is a filterll, and the filterIl includes filter inductors Ly; and Ls. One end of the filter inductor Ly; is connected to the node a, the other end of the filter inductor L,; is connected to one end of the filter inductor L31, the other end of the filter capacitor L31 is connected to the node b, and the one end of the filter inductor L3; and the node c form the output side of the filter.
16 AO 20.06.1082 NL In the third case, FIG. 5 is a schematic structural diagram of the circuit topology in which the filter in FIG. 2 is a filter.
The filter 1s a filter 11, and the filterIl includes filter inductors Lagi, L3o1, and Lag and a filter capacitor Co1. One end of the filter inductor Lo is connected to the node a, the other end of the filter inductor Lay is connected to one end of the filter inductor Lsgq, one end of the filter inductor Lao, and one end of the filter capacitor Co, the other end of the filter inductor Ls; is connected to the node b, the other end of the filter capacitor Co; is connected to the node ¢, and the other end of the filter inductor Lip and the node c form the output side of the filter.
Embodiment 3 This embodiment relates to a control circuit for a boost half-bridge inverter.
The control circuit is applicable to the boost half-bridge inverter in each of the technical solutions described in Embodiment 1 and Embodiment 2. As shown in FIG. 26, the voltage u, on the output side of the filter is used as a feedback voltage, and is compared with a given voltage U,r to obtain an error value, the error value is adjusted by a regulator (the type of the used regulator can be selected based on a requirement, FIG. 26 shows an example of a PID regulator that can be selected in actual application, and a PI regulator, a PD regulator, and the like are not limited by this embodiment and examples enumerated in the accompanying drawings), and then is compared with a triangular wave iy; to generate a pulse signal, and the pulse signal is input into ends B of the power switching transistors Sy and Ss.
Embodiment 4 Based on Embodiment 1 and/or Embodiment 2, this embodiment provides a control method for a boost half-bridge inverter.
Various filters can be selected, and therefore in this embodiment, the working principle/mode of the present invention is analyzed in detail by selecting the filter] as the filter.
When other types of filters are selected, the analysis method is similar.
Bipolar modulation waveforms are input into the ends B of the power switching transistors ‚5; and S». The control method involves single-voltage closed-loop control.
The voltage on the output side of the filter is selected as the feedback voltage, and is
17 AO 20.06.1082 NL compared with the given voltage Us to obtain the error value. The error value is adjusted by the regulator, and then is compared with the triangular wave to generate the pulse signal to control conduction and cut-off of the power switching transistors S; and $>, so that the power switching transistors $; and §; work in a complementary state.
FIG. 9 is a schematic diagram of the modulation waveforms input into the ends B of the power switching transistors Sy and S». FIG. 10 is a schematic diagram of a working mode sequence according to this embodiment. During actual circuit operation, duration of mode 2 is shorter than that of mode 1 and that of mode 3, and can be ignored in analysis of the transformation ratio. For clarity, FIG. 10 is enlarged. Mode 1 FIG. 6 is a schematic structural diagram of a circuit in a working mode 1 in the present invention. When the modulation wave is greater than the carrier, the power switching transistor 54 is controlled to be conducted, 55 is controlled to be cut off, the diodes Dy and D are controlled to be conducted, and D: is controlled to be cut off; the input side, the inductor L,, the diode Dy, and the power switching transistor §; form a loop to charge the inductor L;; and the input side is connected to the direct current power supply Un, the direct current power supply Ui, charges the inductor L; through the power switching transistor S;, and the inductor current i; increases linearly; the power switching transistor Sy, the nodes a and b on the output side, and the diode D» form a loop, and the filter inductor current ir; freewheeling through the diode Do; the capacitor C), the power switching transistor S;, and the nodes a and c on the output side form a loop to supply power to the output side, and the current flowing through the output side increases; and the capacitor C; supplies power to an alternating current side (output side) through the power switching transistor Sy, and the filter inductor current 7; increases. In this case, the output voltage amplitude U,n=+mUci, where m represents a modulation ratio.
18 AO 20.06.1082 NL . U, . i (== =1,) +1, (1) h (3-1) . Ue =U ve D= ta) +i, (1) : (3-2) The freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current, Mode 2 FIG. 7 is a schematic structural diagram of a circuit in a working mode 2 in the present invention.
When the modulation wave is less than the carrier, the power switching transistor $; is controlled to be conducted, S; is controlled to be cut off, the diode D5 is controlled to be conducted, and D: is controlled to be cut off; the input side, the inductor L,, the diode Dy, the capacitors €; and C, and the diode D; form a loop, the inductor L, is in a discharging state, the inductor current iy; decreases to 0, this mode ends, and mode 3 is entered; the power switching transistor $,, the nodes a and b on the output side, and the diode Ds; form a loop, and the filter inductor current 7; ; freewheeling through the diode Ds; and the power switching transistor S,, the nodes a and c on the output side, and the capacitor C: form a loop to supply power to the output side, the capacitor C supplies power to a load on an alternating current side through the power switching transistor S», and the filter inductor current /; 3 Increases. oo U =U =U Co ip, (1)= (t=) +i, (1) t (3-3) , Us, +U , fp (= ~~ (tt +i (1) L (3-4) The freewheeling loop in which the output side (alternating current side) is located is
19 AO 20.06.1082 NL disconnected from the input side (direct current side), so that this topology suppresses a common-mode current.
FIG. 8 is a schematic structural diagram of a circuit in a working mode 3 in the present invention. When the modulation wave is less than the carrier, the power switching transistor ‚5: is controlled to be conducted, S; is controlled to be cut off, the diode Ds is controlled to be conducted, and D: is controlled to be cut off; the power switching transistor Sy, the nodes b and c on the output side, and the diode Ds form a loop; and the power switching transistor S», the nodes a and c on the output side, and the capacitor C: form a loop to supply power to the output side, the filter inductor current 13 continues to increase, and the filter inductor current i> continues flowing through the diode Ds.
. U +U . i (= ——s — 1, +i (1) 3 (3-5) The freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current.
To simplify analysis, the following assumptions are made: (1) All components in the circuit are ideal devices, that is, impact of parasitic parameters is not considered. (2) Two groups of buck unit parameters are completely symmetric. (3) The capacitors C, and C: are large enough, and voltages Uc; and Uc: at both ends of each of the capacitors remain basically unchanged in a switching cycle.
The duty cycle D; of the power switching transistor § varies sinusoidally in each carrier cycle. It is set that in the i" carrier cycle, the duty cycle of the power switching transistor S, or 5; at the moment t; is D;, where m represents a modulation ratio. Based on a regular symmetric sampling rule, the duty cycle can be obtained as follows:
20 AO 20.06.1082 NL D =msin ax, (3-6). Based on volt-second balance of the inductor L;, the following is obtained: UD = Uta U); Ts (3-7), where Di represents the duty cycle corresponding to mode 2. For the inverter circuit in this embodiment, if losses of all the devices in the circuit are ignored, input power is equal to output power, and therefore the following can be obtained: = 2) U nin UND) IK (3-8).
It is assumed that Uc =Uc2=Uc, Um represents the output voltage amplitude, and Usm=mUc. The average input current is equal to the average inductor current, and L, represents the average input current. In other words, 1, =Í, (3-9). The average current value on the inductor L; is as follows: 1D +D,) Lp = 2 (3-10), where hr=UiaDiTs/L,. and represents a current variation of the inductor L;. It can be learned, based on the formulas (3-7) to (3-10), that the relationship between the input voltage and the direct current bus voltage is as follows: 1 16D’T,R,,. Fendt |+ 100 TR 38) Un Lim (3-11), where Di is a valid value, and D;‚=m/ V2 . In this case, the voltage ratio G of the output side to the input side is as follows:
21 AO 20.06.1082 NL G= ng 14855, Uy + 4 (3-12), where Uo represents the voltage amplitude on the output side, Uj, represents the voltage amplitude on the input side, m represents the modulation ratio, Ts represents the modulation cycle, and Ro represents the equivalent impedance value of the load or power grid connected to the output side of the filter. To implement the foregoing working principle, single-voltage closed-loop control is used in the present invention. The output voltage is selected as the feedback voltage, and is compared with the given voltage U. after being multiplied by a specific coefficient, and the error value is adjusted by the regulator, and then is compared with the triangular wave to generate the pulse signal to control conduction and cut-off of the power switching transistors S and S», so that the power switching transistors S; and $: work in the complementary state. Based on the modal analysis in this embodiment, it can be learned that the freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that the topology suppresses the common-mode current and eliminates common-mode interference, and therefore there is no leakage current.
Through the detailed analysis of the working modes in the present invention, in comparison with the conventional dual-buck inverter, the technical solution of the present invention has the following effects: (1) The technical solution of the present invention achieves both an inversion effect and a boost effect, and overcomes the disadvantage that the conventional dual-buck half- bridge inverter can be inverted, but a transformation ratio is reduced, and boosting cannot be implemented. To resolve the buck problem of the conventional dual-buck half-bridge inverter, the inventor of the present invention creatively puts forward the boost half-bridge inverter. Although a conventional dual-buck half-bridge structure with the buck inversion effect is used, a boost inversion effect is achieved. This is contrary to the technical effect achieved by the conventional dual-buck half-bridge converter, and
22 AO 20.06.1082 NL cannot be figured out by an ordinary person skilled in the art by using existing technical means.
(2) In modes 1 to 3 in the technical solution of the present invention, in comparison with the conventional dual-buck half-bridge inverter, the output side is always in a continuous state, the input side (direct current power supply Un) stores energy to the inductor Lj, and the inductor L; outputs energy to the output side, to increase a boost ratio and perform inversion.
The conventional two-stage combination of a DC-DC converter and an inverter can also achieve boost and inversion effects. For example, the first stage is a boost inverter, and the second stage is a full-bridge inverter. This solution has the following technical problems compared with the technical solution of the present invention: (1) In the conventional two-stage combination of a DC-DC converter and an inverter, a matching problem between the output end of the first-stage DC-DC converter and the input end of the second-stage inverter needs to be considered. A filter is usually added between the DC-DC converter and the inverter. The two-stage combination of a DC-DC converter and an inverter includes too many components and there is the filter configured to adjust matching between the DC-DC converter and the inverter, which results in a larger circuit size and a larger loss. The technical solution of the present invention creatively resolves the foregoing technical problem. Compared with the two- stage combination of a DC-DC converter and an inverter, the circuit structure in the present invention includes fewer components, the circuit structure is used as a whole, and there is no matching problem. Therefore, a matching filter does not need to be used, thereby greatly reducing occupied space and costs.
(2) In the conventional two-stage combination of a DC-DC converter and an inverter, in terms of the control circuit, two control loops are often used to control the first-stage DC-DC converter and the second-stage inverter respectively. In addition, in design and control of the two control circuits, the matching problem between the first stage and the second stage needs to be considered for a control effect. Consequently, structures of the
23 AO 20.06.1082 NL control circuits are complex, the design is difficult, design costs are high, the control process is time-consuming, and it is inconvenient to perform operations. The technical solution of the present invention creatively resolves the foregoing technical problem. In view of features of the circuit structure in the present invention, only one control loop is required to control the circuit, and there is no technical problem of matching between control loops, which simplifies the structure of the control circuit, reduces design costs, and results in a convenient control process.
The Chinese patent application (referred to as the prior art 1) with publication No. CN107834886A also achieves both an inversion effect and a boost effect. However, the technical solution of the present invention has the following features compared with the prior art 1: (1) In the circuit topology mechanism of the prior art 1, five power switching transistors are used. The number of power switching transistors used in the present invention is less than that in the prior art 1. The number of components is reduced, circuit costs are reduced, and the loss 1s lower. In terms of the boost gain, although the boost gain achieved by the technical solution of the present invention is lower, the boost gain still belongs to the same boost level as that in the prior art 1.
(2) In modes 1 and 2 of the prior art 1, switching transistors S2 and Sj are alternately conducted, and in modes 3 and 4, S$; and Ss are also alternately conducted. In this case, there may be a shoot through problem. which may cause inversion distortion or even failure. A dead time needs to be added to the control algorithm, which makes the control algorithm complex. However, there is no shoot through problem in the technical solution of the present invention, and no dead time needs to be added, which simplifies the control algorithm. (3) Switching stress of the power switching transistor in the prior art 1 is lower, and is voltages at both ends of a capacitor C;. Switching stress of the power switching transistor in the present invention is larger, is twice that of the prior art 1, and is the sum of voltages of the capacitors C; and C5. It can be learned from that the technical solution
24 AO 20.06.1082 NL of the present invention is not readily figured out from the technical solution of the prior art 1.
(4) In the prior art 1, to reduce the circuit size, the capacitor is a non-polar capacitor, and has a smaller value. In the technical solution of the present invention, to maintain voltage stability, the capacitors C; and C; have larger values. Therefore, it can be learned that the technical solution of the present invention is not readily figured out from the technical solution of the prior art 1.
Table 1 Selection of circuit component parameters Numerical Numerical Parameter Parameter value value Input voltage ce ! ag 45-60 Filter inductors L; and L3/mH | 3
UV Output voltage . p 8 110 Capacitors Cy and Co/uF 100
UIN Rated power . 250 Output capacitor C/uF 5 Ee js Input inductor og 110 Switching frequency f/kHz 20 Li/uH To verify the technical effects of this embodiment, the parameters of the components are selected as shown in Table 1, the circuit topology is constructed on Matalab, and circuit simulation is performed. FIG. 11 shows current waveforms corresponding to the inductors Ly, Lp, and Li. FIG. 12 shows the output voltage waveform. FIG. 13 shows voltage waveforms at both ends of each of the capacitor C| and the capacitor C,. Embodiment 5 The inverter in Embodiments 1-4 can be controlled only through bipolar control, which results in a loop current problem, and increases the loss. When inductance values of Ls and Ls; (10 mH) are about 2% of original inductance values, the loop current is almost 0.
25 AO 20.06.1082 NL However, an output needs to be filtered by a series inductor (10 mH), which further increases the circuit size. To further resolve the loop current problem, this embodiment provides a boost half- bridge inverter. The boost half-bridge inverter includes power switching transistors Si, Sa, and S3, diodes Dy, Da, and Ds, an inductor Lj, and capacitors € and €. As shown in FIG. 14, one end of the inductor L, is connected to one end of the input side, and the other end of the inductor L; is connected to the anode of the diode D; and the end A of the power switching transistor Ss; the cathode of the diode Dy is connected to the end A of the power switching transistor Sj, the cathode of the diode D», and one end of the capacitor Cy; the end C of the power switching transistor Sy, the cathode of the diode Ds, the end C of the power switching transistor Si, and the other end of the input side are connected to a node a; the anode of the diode D: and the end A of the power switching transistor S$» are connected to a node b; the other end of the capacitor C and one end of the capacitor C are connected to a node c; the anode of the diode Ds is connected to the end C of the power switching transistor S» and the other end of the capacitor C+; and the nodes a, b, and c form an output side.
The one end of the input side is connected to the positive electrode of a direct current power supply, and the other end of the input side is connected to the negative electrode of the direct current power supply. Various direct current power supplies can be selected, and can be determined based on a specific application scenario.
As shown in FIG. 15, the output side is connected to the input side of a filter, and the output side of the filter is connected to a load or a power grid. Various filters can be
26 AO 20.06.1082 NL selected. Three filters are enumerated herein to explain and describe content of the technical solutions of the present invention.
In the first case, as shown in FIG. 16, the filter is a filter], and the filter] includes filter inductors L; and L3 and a filter capacitor Co. One end of the filter inductor L: is connected to the node a, the other end of the filter inductor L: is connected to one end of the filter inductor Z3 and one end of the filter capacitor Co, the other end of the filter capacitor Co is connected to the node c, the other end of the filter inductor Lj is connected to the node b, and the one end of the filter capacitor Co and the node c form the output side of the filter. In the second case, as shown in FIG. 17, the filter is a filterll, and the filterH includes filter inductors L;; and L31. One end of the filter inductor LL; is connected to the node a, the other end of the filter inductor L;; is connected to one end of the filter inductor L31, the other end of the filter inductor Ls; is connected to the node b, and the one end of the filter inductor L3; and the node c form the output side of the filter. In the third case, as shown in FIG. 18, the filter is a filter lll, and the filterIll includes filter inductors Lai, Lior, and Lag; and a filter capacitor Co. One end of the filter inductor Lag; is connected to the node a, the other end of the filter inductor Ly is connected to one end of the filter inductor 301, one end of the filter inductor Lao, and one end of the filter capacitor Coy, the other end of the filter inductor Ls; is connected to the node b, the other end of the filter capacitor Co is connected to the node c, and the other end of the filter inductor Lag and the node c form the output side of the filter.
Embodiment 6 This embodiment provides a control circuit for a boost half-bridge inverter. The control
27 AO 20.06.1082 NL circuit is applicable to the boost half-bridge inverter in each of the technical solutions described in Embodiment 5. As shown in FIG. 27, the voltage ,0 on the output side of the filter is used as a feedback voltage, and is compared with a given voltage Uf to obtain an error value, the error value is adjusted by a regulator (the type of the used regulator can be selected based on a requirement, FIG. 27 shows an example of a PID regulator, and a PI regulator, a PD regulator, and the like are not limited by this embodiment and examples enumerated in the accompanying drawings), and then is compared with a triangular wave uy; to generate a pulse signal, and the pulse signal is input into ends B of the power switching transistors Sy, 52, and Sa.
Embodiment 7 In a control method for a boost half-bridge inverter in this embodiment, bipolar modulation waveforms are input into the ends B of the power switching transistors Sj, Ss, and S3. The control method involves single-voltage closed-loop control. The voltage on the output side of the filter is selected as the feedback voltage, and is compared with the given voltage Uys to obtain the error value. The error value is adjusted by the regulator, and then is compared with the triangular wave to generate the pulse signal to control conduction and cut-off of the power switching transistors Si, $2, and Ss. Specifically, the waveforms are shown in FIG. 25, signals input into the ends B of the power switching transistors Si, 52, and Sz are from top to bottom, and the following working modes are included: Mode a FIG. 19 is a schematic diagram of the working status of the circuit topology in mode a. In the positive half cycle in which the output voltage u, is greater than 0, FIG. 28 shows a corresponding sequence diagram. When the modulation wave is greater than the carrier, the power switching transistors $3 and §, are controlled to be conducted, $2 is
28 AO 20.06.1082 NL controlled to be cut off, and the diodes Dy, D», and D3 are controlled to be cut off; the input side, the inductor Ly, and the power switching transistor 53 form a loop; and the direct current power supply U, charges the inductor L; through the power switching transistor S3 to reserve energy;
the power switching transistor Si, the capacitor Cy, and the nodes a and c on the output side form a loop; and the capacitor C; supplies power to the load or power grid on the output side through the power switching transistor S$;. Voltages of the nodes a and c on the output side are voltages Uc; at both ends of the capacitor C.
In this case, the output voltage amplitude is U m=+mUc1, where m represents a modulation ratio.
A freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current,
Mode b Time of the mode is extreme short, and can be ignored in specific analysis.
As shown in FIG. 20, when the modulation wave is less than the carrier, the power switching transistors Si, 52, and Sz are controlled to be cut off, both the diodes D; and Ds are controlled to be conducted, and the diode D: is controlled to be cut off;
the input side, the inductor Ly, the diode Di, the capacitor Cy, the capacitor Cz, and the diode Ds form a loop; the nodes a and c on the output side, the diode Ds, and the capacitor C: form a loop; the direct current power supply Ui, and the inductor L, charges the capacitors C and Cy, the inductor ZL; decreases until the inductor is 0, and mode c is entered; and the capacitor C supplies power to the load or power grid on the output side through the diode Ds.
The freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current
29 AO 20.06.1082 NL side), so that this topology suppresses a common-mode current.
Mode ¢ As shown in FIG. 21, when the modulation wave is less than the carrier, the power switching transistors Sy, Sa, and Ss are controlled to be cut off, the diode Djs is controlled to be conducted, and the diodes D, and D: are controlled to be cut off; and the current of the inductor Ly is 0, the inductor L; is in a discontinuous current state, and the nodes a and c on the output side, the diode D3, and the capacitor C: form a loop.
A freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current.
Mode d FIG. 22 shows a working status of the circuit topology in mode d.
In the negative half cycle in which the output voltage u, is less than 0, FIG. 29 is a corresponding sequence diagram.
When the modulation wave is greater than the carrier, the power switching transistors S; and Ss are controlled to be conducted, S; is controlled to be cut off, and the diodes Dy, D», and D5 are controlled to be cut off;
the input side, the inductor L,, and the power switching transistor $3 form a loop; the direct current power supply U, charges the inductor L; through the power switching transistor $3; the power switching transistor S», the nodes b and c on the output side, and the capacitor C: form a loop; the output voltage amplitude is U,‚m=-mUc;, where mm represents a modulation ratio; and the capacitor C: supplies power to the load or power grid on the output side through the power switching transistor S>. The freewheeling loop in which the output side (alternating current side) is located is disconnected from the
30 AO 20.06.1082 NL input side (direct current side), so that this topology suppresses a common-mode current, Mode e Time of the mode is extreme short, and can be ignored in specific analysis. As shown in FIG. 23, when the modulation wave is less than the carrier, the power switching transistors Si, 55, and 5: are controlled to be cut off, and all of the diodes D;, D>, and Ds are controlled to be conducted; the input side, the inductor L,, the diodes D; and Ds, and the capacitors Cy and C: form a loop; the direct current power supply U, and the inductor L; charge the capacitors C and C,, the inductor L; decreases until the inductor is 0, and mode f is entered; the diode Ds, the capacitor Cy, and the nodes b and c on the output side form a loop; and the capacitor C supplies power to the load or power grid on the output side through the diode Ds. The freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current.
Mode f As shown in FIG. 24, when the modulation wave is less than the carrier, the power switching transistors Sy, Ss, and Ss are controlled to be cut off, the diodes D; and Ds are controlled to be cut off, and the diode D: is controlled to be conducted; the diode Da, the capacitor Cy, and the nodes b and c on the output side form a loop; and the capacitor C supplies power to the load or power grid on the output side through the diode Da. The freewheeling loop in which the output side (alternating current side) is located is disconnected from the input side (direct current side), so that this topology suppresses a common-mode current,
31 AO 20.06.1082 NL The relationship between the input voltage amplitude and the output voltage amplitude in this embodiment is calculated as that in Embodiments 2-4. In comparison with the conventional boost inverter, the transformation ratio is high, and the adjustable range is large.
By using the control method described in this embodiment, the output voltage u, of good quality, high anti-interference performance, and good stability are obtained, and beneficial effects are the same as those in Embodiment 4. In addition, the loop current problem is eliminated.
Based on the modal analysis in this embodiment, it can be learned that the freewheeling loop in which the output side (alternating current side) is disconnected from the input side (direct current side), so that the topology suppresses the common-mode current and eliminates common-mode interference, and therefore there is no leakage current.
When working, the boost inverter described in this embodiment works in different modes in the positive half cycle in which the output voltage is greater than 0 and the negative half cycle in which the output voltage is less than 0 to form different boost inverter circuits, as shown in FIG. 25. The control signal of the power switching transistor $; is a high-frequency switching signal.
The power switching transistor S2 works in a high-frequency state in the positive half cycle in which the output voltage 4, is greater than Ô, and is in a cut-off state in the negative half cycle.
The power switching transistor $3 works in the high-frequency state in the negative half cycle in which the output voltage u, is less than 0, and is in the cut-off state in the positive half cycle.
The power switching transistors Sz and $3 work in a low-frequency state in a half cycle, reducing the switching loss.
After comparison, the working principle of the boost half-bridge inverter in this embodiment is different from that of the conventional dual-buck half-bridge inverter and the boost half-bridge inverter provided in Embodiment 1. When unipolar
32 AO 20.06.1082 NL modulation is used, there is no loop current in this embodiment, but a loop current occurs in both the conventional dual-buck inverter and the boost half-bridge inverter in Embodiment 1. In this embodiment, the loop current problem is resolved by using the half-cycle modulation method {as shown in FIG. 25, the power switching transistor S» and S3 each work in a half cycle).
The foregoing description is merely preferred embodiments of the present invention and description of the used technical principles. A person skilled in the art should understand that the invention scope involved in the present invention is not limited to a technical solution formed by a specific combination of the foregoing technical features, but should further include other technical solutions formed by any combination of the foregoing technical features or equivalent features without departing from the concept of the present invention, for example, technical solutions formed by replacing the foregoing features with (but not limited to) the technical features with similar functions disclosed in the present invention.

权利要求:
Claims (12)
[1]
A boost half-bridge inverter, comprising current switching transistors S; and Sz, diodes D i, D i and Dy, a coil L i, and capacitors C; and C5, wherein one end of the coil L; 1s connected to one end of the input side, and the other end of the coil L; is connected to the anode of the diode Dy; the cathode of the diode D; is connected to the end A of the current switching transistor S 1, the cathode of the diode D; and one end of the capacitor Cy; the end C of the current switching transistor § i, the cathode of the diode D; and the other w end of the input side are connected to a node a; the anode of the diode D; and the end A of the current switching transistor S: is connected to a node b; the other end of capacitor C; and one end of the capacitor C: is connected to a node c; the anode of the diode D; is connected to the end C of the current switching transistor S; and the other end of the capacitor Cs; and nodes a, b and c form the output side.
[2]
The boost half-bridge inverter according to claim 1, wherein one end of the input side is connected to the positive electrode of a DC power supply, the other end of the input side is connected to the negative electrode of the direct power supply, the output side is connected to the input side of a filter, the output side of the filter is connected to a load or an electricity grid and the current switching transistors §; and S $; Be IGBTs or MOSEFETs.
[3]
3. A boost half-bridge inverter, containing transistor transformers S ;, S; and $ 3, diodes Dy, D2 and Dj, a coil L 1, and capacitors C; and C:, wherein one end of the coil L; is connected to one end of the input side, and the other end of the coil L; is connected to the anode of the diode D; and the end A of the current switching transistor S3; the cathode of the diode D; is connected to the end A of the current switching transistor, the cathode of the diode D; and one end of the capacitor Cp;
The end C of the current switching transistor S i, the cathode of the diode D i, the end C of the current switching transistor 53 and the other end of the input side are connected to a node a; the anode of the diode D5 and the end A of the current switching transistor S; be connected to a node b; the other end of capacitor C; and one end of the capacitor C: is connected to a node c; the anode of the diode D; is connected to the end C of the current switching transistor S »and the other end of the capacitor C; and the nodes a, b and c form an output side.
[4]
The boost half-bridge inverter according to claim 3, wherein one end of the input side is connected to the positive electrode of a DC power source, the other end of the input side is connected to the negative electrode of the DC power source, the output side is connected to the DC power supply. input side of a filter, the output side of the filter is connected to a load or an electricity grid, and the current switching transistors S ;. S $ »and S; Be IGBTs or MOSEFETs.
[5]
Boost half-bridge converter according to claim 2 or 4, wherein the filter is a filter Lis, the filter I filter coils L; and L; and a filter capacitor Co comprises one end of the filter coil L; is connected to the node a, the other end of the filter coil L; is connected to one end of the filter coil Lz and one end of the filter capacitor Co, the other end of the filter capacitor Co is connected to the node c, the other end of the filter coil L; is connected to the node b, and one end of the filter capacitor Co and the node c form the output side of the filter.
[6]
Boost half-bridge inverter according to claim 2 or 4, wherein the filter is a filter II, the filter I filter coils Ly; and Lz; comprises one end of the filter coil Ly; is connected to the node a, the other end of the filter coil L ;; is connected to one end of the filter coil L3; the other end of the filter capacitor L31 is connected to node b and one end of the filter coil L3; and node c is the output side of the filter.
35 AO 20.06.1082 NL
[7]
Boost half-bridge inverter according to claim 2 or 4, wherein the filter is a filter HI, the filter HI is filter coils Loo; Lip; and Lg; and a filter capacitor Co. one end of the filter coil L> 9; is connected to node a, the other end of the filter coil Lay; is connected to one end of the filter coil L39 i, one end of the filter coil Ly; and one end of the filter capacitor Cg, the other end of the filter coil L39; connected to the node b, the other end of the filter capacitor Co; is connected to the node c and the other end of the filter coil L49; and the node c forms the output side of the filter.
[8]
8. The boost half-bridge converter driving circuit of claim 2, wherein the voltage on the output side of the filter is used as the feedback voltage and compared with a given voltage U; to obtain an error value in which the error value is adjusted by a controller, and then compared with a triangular wave to generate a pulse signal, and the pulse signal is inputted to ends B of the current switching transistors $; and Ss.
[9]
A driving method for the boost half-bridge inverter according to claim 1, 2 or 8, wherein bipolar modulation waveforms are inputted to the ends B of the current switching transistors S; and S », and the following operating modes are included: When the modulation wave is larger than the carrier wave, the current switching transistor §; is driven to be conducted, 52 is driven to be cut off, the diodes D; and D> are driven to be guided and D3 is driven to be cut off; form the input side, the coil L1, the diode D; and the current switching transistor S; a loop around the coil L; to charge; the current switching transistor S1, the nodes a and b on the output side, and the diode D- form a loop; and the capacitor Ct forms the current switching transistor $; and the output side nodes a and E loop to supply power to the output side; or when the modulation wave is smaller than the carrier, the current switching transistor S2 is driven to be conducted, $; is driven to be cut off, the diode Dz is driven to be conducted and D; is becoming
36 AO 20.06.1082 GB guarded to be cut off; form the input side, the coil L i, the diode Dy, the capacitors C and C i and the diode D i; a loop; the current switching transistor Sa, the nodes a and b on the output side, and the diode Dz form a loop; and the current switching transistor S1 form the output side nodes a and c, and the capacitor C; a loop to supply power on the output side; or when the modulation wave is smaller than the carrier, the current switching transistor S $; is driven to be led, $ 7 is driven to be cut, the diode Dj; is controlled to be guided and D> is controlled to be cut off; form the current switching transistor $>, the nodes a and b on the output side, and the diode D; a loop; and the current switching transistor S2, the nodes a and c on the output side, and the capacitor C form a loop to supply current on the output side.
[10]
A driving method for the boost half-bridge converter according to claim 9, wherein the voltage ratio G from the output side to the input side is as follows: G = m "gs hsl, U dN 5 where; Uom represents a voltage amplitude on the output side, Uj , represents a voltage amplitude on the input side, m represents a modulation ratio, Ts represents a modulation cycle, and Ro represents an equivalent impedance value of the load or utility grid connected to the output side of the filter.
[11]
Driving kit for the boost half-bridge inverter according to claim 4, wherein the voltage on the output side of the filter is used as the feedback voltage and is compared with a given voltage Ue to obtain an error value where the error value is adjusted by a controller and then compared with a triangular wave to generate a pulse signal, and the pulse signal is input to the ends B of the current switching transistors SS1 and Ss.
[12]
Driving method for the boost half-bridge converter according to claim 3,
37 AO 20.06.1082 GB 4 or 11, where unipolar modulation waveforms are input to the ends B of the current switching transistors S ;, S2 and S ;, and the following operating modes are included: in the positive half cycle where the output voltage i, is greater then 0, when the modulation wave is larger than the carrier wave, the switching transistors current S $; and §; are directed to be guided, §; is driven to be cut off and the diodes D1, D2 and Dz are driven to be cut off; form the input side, the coil L; and the current switching transistor S; a loop; and the current switching transistor S i forms the capacitor C; and the nodes a and c on the output side are a loop; or when the modulation wave is smaller than the carrier, the current switching transistors S1, S2, and $; driven to be cut off, both diodes D; as Dj; driven to be conducted and becomes the diode D; directed to be cut off; the input side, the coil L, the diode D i, the capacitor C i, the capacitor C i, and the diode Dz form a loop; and the nodes a and c on the output side form the diode D; and the capacitor Cs is a loop; or when the modulation wave is smaller than the carrier, the current switching transistors becomes $ 1, S2 and $; driven to be cut off, the diode D; controlled to be conducted and the diodes become D; and D; controlled to be cut off: the nodes a and c on the output side form the diode D; and the capacitor C; a loop; or in the negative half cycle in which the output voltage u i is less than 0, when the modulation wave is greater than the carrier wave, the current becomes switching transistors S2 and S; driven to be conducted, S7 is driven to be cut off and the diodes D i, D; and D; directed to be cut off; form the input side, the coil L; and the current switching transistor transistor S3 is a loop; and the current switching transistor S1 form the output side nodes b and c and the capacitor C; a loop; or when the modulation wave is smaller than the carrier, the current switching transistors S1, S »and 3 are driven to cut off.
38 AO 20.06.1082 NL are, and are all diodes D1, D2 and D3 driven to be conductive; the input side, the coil L i, form the diodes D; and Ds, and the capacitors C and C: a loop; and form the diode D i, the capacitor C; and the nodes b and c on the output side a loop; or when the modulation wave is smaller than the carrier, the current switching transistors become S1, $ 2 and S; driven to be cut off, the diodes D; and D3 is driven to be cut off and the diode D> is driven to be led; and form the diode D i, the capacitor C; and the nodes b and c on the output side loop.

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同族专利:

公开号 | 公开日

NL2025812B1|2020-12-29|

CN110098759B|2020-05-05|

CN110098759A|2019-08-06|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

CN107834886A|2017-12-08|2018-03-23|安徽工业大学|A kind of single-stage boost inverter and its control method|

JP2003111393A|2001-09-28|2003-04-11|Toshiba Corp|Booster, power converter, and household electrical appliance|

CN102437764B|2011-10-09|2014-01-01|西安爱科赛博电气股份有限公司|Seven-electrical level DC-AC converter|

CN205407612U|2016-03-09|2016-07-27|浙江大学城市学院|High power factor recommends DC power supply topology circuit|

CN207691703U|2018-01-24|2018-08-03|胡炎申|A kind of DC/AC modules of photovoltaic generating system|

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优先权:

申请号 | 申请日 | 专利标题

CN201910514920.8A|CN110098759B|2019-06-14|2019-06-14|Control method of boost half-bridge inverter|

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